Linear Low-Dropout Regulator (Output Voltage 0.9V)

Overview

1-VIA’s VSCOM4L400ALDO0V9 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulation across a wide range of input and output voltages (0.81-1.02V, 8 configurations with 30mV trimmability in each configuration) implemented in TSMC12/16nm CMOS FinFET technology.

The regulator architecture provides high Power Supply Rejection (PSR) and low noise making it suitable for analog and RF applications.

Block Diagram

Linear Low-Dropout Regulator (Output Voltage 0.9V) Block Diagram

Applications

  • Artificial Intelligence (AI)
  • Internet of Things (IoT)
  • Medical
  • Analogue-to-Digital Converter (ADC)
  • RF ASICs
  • Automotive
  • Wireless
  • Digital-to-Analog Converter (DAC)
  • Mixed-signal ASICs
  • SoCs

Deliverables

  • Datasheet
  • Characterization report
  • Layout view (GDSII)
  • Abstract view (LEF)
  • Behavioural model (VerilogA)
  • Integration guidelines and support

Technical Specifications

Foundry, Node
TSMC 12/16nm CMOS FinFET
TSMC
Pre-Silicon: 12nm , 16nm
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Semiconductor IP