The LDPC decoder product suite has been specifically designed as flexible IP to address the unique challenges of 5G NR across all use cases covered by the current standards, deliver market leading performance and efficiency, and be easily integrated into designs.
LDPC Encoder / Decoder for 3GPP 5G NR
Overview
Key Features
- Complete implementation of the LDPC part of TS 38.212 with optional transport block level processing
- Improved BLER and no error floors – meets strictest requirements for uRLLC
- Proven across muti vendor FPGA and ASIC implementations
- Highly configurable for a wide range of applications
- Design optimised for 5G NR, outperforming generic LDPC decoder solutions
- Configurable to support maximum throughputs and minimum timing requirements for all numerologies and across all HARQ transmissions
- Very low latency – meets requirements for uRLLC
- Efficient design – saves device area
- Low power – half the energy per bit of competitors
- Easy to integrate
Block Diagram
