Latch-Up Detector

Overview

The ODT-LUP-2I3O-7T-A1 is a latch-up detection solution that can support integration into advanced FinFET process nodes such as N7.
The IP works in conjunction with applicable PCB monitoring points solution includes both internal and PCB elements with 2 analog inputs and from 1-3 digital output ports. A threshold with 5mV minimum sensitivity and 100mV minimum operating range can be configured with 1mV increments. Programmable filtering is used to reduce the impact of glitches and false positives, and interrupts are provided when a failure occurs. The IP can be configured via an APB interface.

Key Features

High level Latch-up Protection Solution
Detect down to 500mA latch up current
Reaction time on the range of 100us to cut-down current
Configuration to adapt to PVT conditions for each chip
Filtering of activity-based changes
Minimize power loses
No additional latch-up risk to the system
Additional features will include autozero / offset calibration, programmable glitch filtering, programmable thresholds, and persistent interrupt generation.

Benefits

High Performance Low Power, Low Area

Applications

PCB voltage level monitoring
Current spike detection
Space applications

Deliverables

Datasheet
Hard Macro (GDSII)
Characterization Report (as applicable)
Abstract View (LEF) for top level connectivity
Integration and Customer Support

Technical Specifications

Foundry, Node

TSMC 7nm

Maturity

Design Kit Ready

Availability

Now

TSMC

Pre-Silicon: 7nm

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