Navigating the Complexity of Address Translation Verification in PCI Express 6.0
Geeta Arora, Cadence
Vendor:
Microtronix Datacom Ltd.
Category:
PCI Express
Lancero Scatter-Gather DMA Engine for PCI Express
The Lancero Scatter-Gather DMA Engine for PCI Express provides a Target Bridge and/or a Descriptor Bridge SGDMA solution for PCI …
Overview
The Lancero Scatter-Gather DMA Engine for PCI Express provides a Target Bridge and/or a Descriptor Bridge SGDMA solution for PCI Express endpoints. The IP connects seamlessly to Altera PCI Express Hard IP cores, providing a transparent high-speed data path over PCI Express.
The Lancero Design Kit offers a complete end-to-end hardware IP core and software driver solution for exchanging full-duplex, high bandwidth streaming data over PCI Express with your embedded processor. The simple, easy to use Altera SOPC interface of the Lancero provides developers with the ability to easily integrate their custom FPGA logic with PCI Express and Linux/Windows applications without worrying about having detailed working knowledge of PCIe.
It is available in two basic configurations; Lancero Target Bridge and Lancero Descriptor Bridge with a SGDMA IP Core. The Target Bridge configuration is ideal for small PCI express endpoints, which just require simple register access. The Descriptor Bridge SGDMA configuration provides for very high-speed DMA transfers with minimal CPU overhead.
Device Drivers
The Lancero device drivers use the operating system standard interface, either Linux IEEE POSIX or the Windows programming interface. The drivers provide one character device interface for the control bus, one character device interface for SGDMA and one character device interface for user interrupts.
A major benefit of the Lancero SGDMA solution is its ability to perform large SGDMA transfers directly to and from the users application buffers, without the need for in-kernel copies associated with regular DMA controllers.
By providing a control bus and data bus with SGDMA engines, developers can now process high performance data transfers between the FPGA logic and your Linux application making this an ideal solution for:
Hardware designers using the Avalon MM and ST bus interfaces from Altera
Software designers: only require Linux read/write() or Windows Read/WriteFile() functions
The Lancero Design Kit offers a complete end-to-end hardware IP core and software driver solution for exchanging full-duplex, high bandwidth streaming data over PCI Express with your embedded processor. The simple, easy to use Altera SOPC interface of the Lancero provides developers with the ability to easily integrate their custom FPGA logic with PCI Express and Linux/Windows applications without worrying about having detailed working knowledge of PCIe.
It is available in two basic configurations; Lancero Target Bridge and Lancero Descriptor Bridge with a SGDMA IP Core. The Target Bridge configuration is ideal for small PCI express endpoints, which just require simple register access. The Descriptor Bridge SGDMA configuration provides for very high-speed DMA transfers with minimal CPU overhead.
Device Drivers
The Lancero device drivers use the operating system standard interface, either Linux IEEE POSIX or the Windows programming interface. The drivers provide one character device interface for the control bus, one character device interface for SGDMA and one character device interface for user interrupts.
A major benefit of the Lancero SGDMA solution is its ability to perform large SGDMA transfers directly to and from the users application buffers, without the need for in-kernel copies associated with regular DMA controllers.
By providing a control bus and data bus with SGDMA engines, developers can now process high performance data transfers between the FPGA logic and your Linux application making this an ideal solution for:
Hardware designers using the Avalon MM and ST bus interfaces from Altera
Software designers: only require Linux read/write() or Windows Read/WriteFile() functions
Key features
- PCIe I/O performance: 200 MB/s x1 Gen 1 up to 3360 MB/s x8 Gen 2
- Easily connect logic and high-speed I/O peripherals to PCI Express
- Target Bridge supports Avalon Memory Mapped custom logic
- SGDMA Engine supports Avalon Streaming burst access devices
- SGDMA controller transfers data directly to/from Linux/Windows User Applications
- Uses simple Linux read/write(), or Windows Read/WriteFile() functions to perform SGDMA
- Zero host CPU overhead: SGDMA transfers eliminates need for duplicate in-kernel transfers
- Supports asynchronous and multi-threaded I/O to completely remove inter-transfer latencies
- Low LE resource count for on-chip fabric logic and memory
- Reference designs for Altera Cyclone IV GX, Arria II GX and Stratix IV GX Dev Kits
- Drivers support x86, PowerPC, ARM, Intel i7, Intel e600/e6x5 and other processors
- Supports Cyclone IV GX, Stratix IV GT/GX, Arria II GX, Hardcopy IV GX devices
- Target Applications
- The Lancero IP core is targeted at embedded systems utilizing PCIe for high-speed I/O interfaces.
- Medical imaging and print imaging
- Wireless radio
- High bandwidth data acquisition and logging
- NAS storage systems, solid state and memory storage systems
- Video surveillance, video capture, graphics framebuffer overlays, digital signage
Block Diagram
1597604 block diagram
Benefits
- The Lancero IP core is targeted at embedded systems utilizing PCIe for high-speed I/O interfaces.
- Boost the I/O performance of your Linux/Windows platform using the easy-to-use Lancero Scatter-Gather Direct Memory Access Engine IP core solution for PCIe interfaces.
What’s Included?
- SystemVerilog RTL encrypted netlist or full source
- Simulation models
- Linux drivers: DLL or source
- Documentation
- Quartus reference designs for:
- Altera Cyclone IV GX
- Arria II GX
- Stratix IV GX
- Terasic DE4 Dev board
- Technical support
Video
Video 1
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
1597604
Vendor
Microtronix Datacom Ltd.
Provider
Microtronix Datacom Ltd.
HQ:
Canada
Microtronix began as a design and embedded engineering firm for custom networking equipment for the Telco marketplace, pioneering the X25 protocol. Today, Microtronix uses these same engineering skills to develop and support their own line of embedded products, specializing in the rapid development of FPGA based hardware, IP cores, printed circuit board, and software solutions for embedded products. Microtronix provides a turnkey design-development service, with proven expertise in taking products from initial concept through to production.
Microtronix also provides embedded engineering design services for these technologies either on an hourly basis or through a fixed price quotation.
By design, all Microtronix solutions are engineered to be cost effective and exceed their requirements for service, quality, and function.
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Frequently asked questions about PCIe IP cores
What is Lancero Scatter-Gather DMA Engine for PCI Express?
Lancero Scatter-Gather DMA Engine for PCI Express is a PCI Express IP core from Microtronix Datacom Ltd. listed on Semi IP Hub.
How should engineers evaluate this PCI Express?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.