The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channels between transmit and receive cores. This core is not intended to be used standalone and should only be used only in conjunction with the JESD204 core.
Note: This core is provided as standalone IP for use in the JESD204 IP example design only.
JESD204 PHY
Overview
Key Features
- Designed to JEDEC® JESD204B
- Supports 1 t0 12 lane configurations
- Supports Subclass 0, 1, and 2
- Physical layer functions provided
- Supports trasceiver sharing between TX and RX cores
Technical Specifications
Related IPs
- JESD204
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation
- LPDDR5X/5/4X PHY - TSMC N5A for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC N5 X8, North/South (vertical) poly orientation
- UCIe-S PHY for Standard Package (x16) in SS SF5A, North/South Orientation