World-class, industry-leading, highly scalable, silicon- and PHY-agnostic IP core with 116 Gbps line rate, interoperability tested with leading Serdes providers
Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload. The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. Our Interlaken controller supports up to 2.6 Tbps high-bandwidth performance and comes with an integrated Media Access layer.
The Interlaken Controller can be widely used in chip-to-chip transfers, it has an extensive feature-set available and allows scalability in number of logic channels (up to 2048), lanes (up to 48) and lane speed (up to 56 Gbps). The IP core is heavily tested in SystemVerilog random regression environment
The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. It delivers all features of the standard and includes Retransmission and RS FEC Standard extensions.
The solution consists of combined TX and RX data paths with PCS, MAC and Protocol layers included. In Band Flow control over the data lanes and Out of Band Flow control over a separate interface are available.
Error recovery is made possible via the Retransmit extension. Error correction and PAM 4 encoding with Line rates up to 116Gbps is made possible with the RS FEC extension.
