Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload. The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. Our Interlaken controller supports up to 2.6 Tbps high-bandwidth performance and comes with an integrated Media Access layer.
The Interlaken Controller can be widely used in chip-to-chip transfers, it has an extensive feature-set available and allows scalability in number of logic channels (up to 2048), lanes (up to 48) and lane speed (up to 56 Gbps). The IP core is heavily tested in SystemVerilog random regression environment.
Interlaken Controller
Overview
Key Features
- Richly Featured
- MAC layer with fast AMBA CXS interface
- PCS layer highly configurable with up to 48 lanes
- Multi-lane configurations, up to 48 lanes
- 64B 67B encoding/decoding supported
- Supports up to 2048 logic channels
- Programmable Meta Frame lengths
- Programmable Interlaken Bursts: Short from 32 and Max up to 1024 Bytes
- Flow control support
- Mode of operation: Packet mode and Interleave mode supported
- Re-transmit
- Interlaken Dual Calendar
- Look-Aside
- FEC support
- Bytes
- Flow control support
- Mode of operation: Packet mode and Interleave mode supported
- Retransmit support
- Dual Calendar support (optional)
- Look-Aside support (optional)
- FEC support (optional)
- Easy to use
- Solid documentation including integration guide
- Easy to use RTL test environment
- No special software required
- Strong engineering support for bring-up
- Solid
- System Verilog random regression tested
- Lint/CDC checked
- Silicon Agnostic
- Targeting both ASICs and FPGAs
Block Diagram
Deliverables
- The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Test Report
- Synopsys SGDC Files
- Synopsys Lint, CDC and Waivers
Technical Specifications
Availability
Available