Interlaken Communication Controller

Overview

Flowgic's Interlaken IP core is an efficient implementation of Interlaken Protocol version 1.1. Interlaken IP core is designed for flexibility, robustness, scalability and is available in 64(10-25 Gb/s), 128(20-25Gb/s), 256(40+ Gb/s) bit datapath variants.

Key Features

  • Up to 8 lanes and each lane operating at data rates up to 6.25 Gbs
  • Link resiliency with support for operation with fewer lanes
  • Support for up to 256 channels
  • Implements out-of-band and in-band flow control
  • Optional full-packet mode support
  • Insertion of BCW/ICW and packet delineation using BCW/ICW
  • Additional ICW insertion to meet BurstShort
  • Implements rate-matching logic with token buckets
  • Efficient scheduling of packets from different channels
  • 64b/67b encoding/decoding
  • Set/reset scrambler
  • Metaframing/deframing
  • Simple system-side interface
  • Optional gear box to work with SerDes with 32 bit interfaces
  • Lane-to-lane deskew logic that can handle up to 107 UI skew
  • Extensive statistics
  • Comprehensive error reporting/handling
  • Per-lane test patterns

Benefits

  • Low Gate Count
  • Flexible Design
  • Designed for Reuse & Testability
  • Proven Design Methodology
  • Customization Options

Block Diagram

Interlaken Communication Controller Block Diagram

Deliverables

  • Functional Specification
  • RTL Database
  • Functional Verification Environment
  • Synthesis Scripts
  • Timing Report
  • User Guide

Technical Specifications

Maturity
Stable
Availability
Immediate
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Semiconductor IP