Intelligent Sensor and Power Management Design Platform

Overview

Key Features

• Smart Power Subsystem
  • Fault detection & on/off control: monitors battery and power supply levels, turns off external battery FET in fault condition, turns system on/off based on power button
  • Buck regulator for ASIC I/O and external components, extends battery life
  • LDO Linear regulator for low-noise analog supply
  • Buck regulator for ASIC digital core in operational mode
  • Power control: manages operational/standby state and controls regulators
  • 900MHz RF Energy Harvester and Rectifier module
  • RC/Xtal oscillator: Clock oscillator for ASIC, low-frequency RC for standby
  • Power-on reset: Reset system when power applied or after fault cleared
  • Ext clock/reset buffer: Provides buffered clock and reset signals to external components
  • Bandgap reference: Provides references for regulators, oscillator, DAC, and other circuits
  • JTAG TAP: Digital test access point
  • Analog test control: Controls test mode and selects analog test points to drive test pads
• Sensor AFE
  • SAR ADC for higher speed conversion
  • Temperature Sensor
  • Three input channel PGAs
  • Programmable Signal Conditioning DSP
• MCU Subsystem
  • MCU core: RISC-V, ARM or ColdFire (or ASTC-8051 if memory and performance requirements allow)
  • Debug control: Register/memory access, run/step, trace, etc, accessed through JTAG or SMBus
  • Watchdog timer: For firmware time-out reset
  • Tick timer: For firmware task scheduling
  • Interrupt controller: Manages interrupts from I/O blocks
  • Firmware flash: For code storage, loaded at product assembly, field upgradeable
  • Data SRAM: For firmware data
  • Signal SRAM: For DSP data to/from external codec, to/from DSP data path, and accessible by MCU core
  • DSP data path: Co-processor for MCU for DSP operations
  • DMA controller: Transfers data between I/O blocks, DSP data path and signal SRAM
  • SPI, I2C master and slave interfaces
  • I3C Slave interface
  • GPIO

Benefits

• By key benefit of the IQonIC Works ISP design platform is that provides a complete ASIC design solution, not peacemeal IP blocks, but the entire range of core analog and digital design blocks required to design and implement an edge based ASIC application. All ISP IP blocks have been designed, integrated and verified together in a reference ASIC architecture and design platform for rapid deployment to an ASIC project and for rapid ASIC design as an ISP ASIC derivative. From the IQonIC Works ISP platform to a customer application specific ASIC requires only the addtion of application specific IP and a custom derivative integration.
• Together with a virtual prototyping flow for hardware and software development and verification, and a streamlined flow for deployment to an ASIC project, the IQonIC Works ISP provides a very fast path for design from application specific requirements to a new ASIC.
• ASTC enables a new ASIC project to be executed within the cost budgets and time lines of an ASIC derivative project.

Block Diagram

Applications

• The IQonIC Works ISP design platform is targeted for edge based embedded applications, i.e. localized intelligent sensing for monitoring, processing, and control, supporting both ASIC- or FPGA-based implementations, including for
  • IoT Monitoring and Control
  • Wearables
  • Healthcare Patient Monitoring and Tracking
  • Consumer Electronics
  • Industrial Automation
  • Home Automation

Deliverables

• The following list of deliverables are included:
  • Datasheet
  • ISP Virtual Platform and baseline SW drivers
  • Platform and module RTL
  • Top level and module schematics
  • Digital and Chip level AMS verification environment and test cases
  • Module Test Suites
  • Integration Guide

Technical Specifications