Intel® Precision Time Protocol Servo (Intel® PTP Servo) FPGA IP

Overview

Coordinate the actions of disparate electronic systems that must be synchronized in time with Intel® PTP Servo, which employs hardware timestamping of packets and can achieve sub-microsecond accuracy to address the needs of synchronization requirements across various applications.

The Intel PTP Servo IP Addresses Time Synchronization Requirements in Network Applications by:

  • Controlling the system clock to achieve synchronization with a reference (PTP grandmaster) time source.
  • Deploying sophisticated feedback mechanisms to adjust the system clock frequency and phase to minimize the offset between the local clock and the reference (PTP grandmaster) time source.
  • Offering superior performance in partial timing support (PTS) networks relative to open-source servos.
  • Supporting FTS and PTS networks (for example, 5G O-RAN Networks).
  • Providing a DCS/PLL-agnostic open-source solution.
  • Maintaining compatibility with portable timing solutions across Intel FPGAs with HPS.

Key Features

  • Precision Clock Synchronization
  • Monitoring and Diagnostics
  • Advanced Metrics
  • Configurable for Application Requirements
  • Works with ptp4l Open-source IEEE 1588 Stack
  • Packet Delay Variation (PDV) Filtering
  • Compliant with ITU Recommendations for PTS, FTS and PTP-unaware Networks

Block Diagram

Intel® Precision Time Protocol Servo (Intel® PTP Servo) FPGA IP Block Diagram

Technical Specifications

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Semiconductor IP