Polybus offers a family of InfiniBand Link Layer Cores ranging from a Single Data Rate 4X core (10GBit/Second) to a Quad Data Rate 8X core (80GBit/second). All Link Layer cores are available for both Xilinx and Altera FPGAs as well as for ASIC applications.
There are three members of the Link Layer family. The SDR Link Layer Core is the smallest core, it operates at 125 MHz and supports bidirectional speeds of 10GBits/second in each direction. Customers are currently using the SDR core in Xilinx Virtex2P, Xilinx Virtex4FX. Altera Stratix2GX and ASICs. The SDR core can operate in the lowest speed grades of the Virtex4FX (-10) and the Stratix2GX (-5).
The DDR (Double Data Rate) Link Layer Core operates at 250 MHz and supports bidirectional speeds of 20GBits/second. The DDR core requires a 5 GHz SerDes. Customers are using the DDR core in Xilinx Virtex4FX, Altera Stratix2GX and in ASICs. The DDR core requires the middle speed grades of the the Virtex4FX (-11) and the Stratix2GX (-4).
The newest memory of the Polybus core family is the QDR (Quad Data Rate) Link Layer Core. The QDR cores supports 8X operation at DDR speeds (40GBits/Second) in FPGAs at 250 MHz and 8X QDR speeds (80Gbits/Second) at 500 MHz in ASICs. The QDR core requires the highest speed grade Stratix2GX (-3). The RTL for the QDR core is available now, it is targeted at the Virtex5FXT and Stratix3 families which should be available in Q3 2007.
InfiniBand Link Layer Cores
Overview
Key Features
- SDR 4X InfiniBand Link Layer Core
- 10 Gbit/second
- 64 bit parallel interfaces
- 1X, 4X operation
- Link initialization and training
- Link layer flow control
- CRC generation and checking
- Protocol error and packet length checking
- Programmable Flow Control Period
- Dynamic Flow Control Mechanism
- Available for 1, 2 & 4 Virtual lanes
- Supports internal and external SerDes.
- Very low latency
- Fully portable, FPGA and ASIC compatible.
- IBA Rev 1.1 compatible
- Supports Xilinx Virtex2P, Virtex4FX-10 and Altera Stratix2GX
- Proven design, shipping in FPGAS and ASICs
- 125MHz clock
- DDR 4X InfiniBand Link Layer Core
- 20 Gbit/second
- 64 bit parallel interfaces
- 1X, 4X operation
- Link initialization and training
- Link layer flow control
- CRC generation and checking
- Protocol error and packet length checking
- Programmable Flow Control Period
- Dynamic Flow Control Mechanism
- Available for 1, 2 & 4 Virtual Lanes
- Supports Xilinx, Altera and ASIC SerDes
- Very low latency
- Fully portable, FPGA and ASIC compatible.
- IBA Rev 1.2 compatible
- Supports Xilinx Virtex4FX-11, Altera Stratix2GX-4.
- Proven design, running in FPGAS and ASICs
- 250MHz clock
- QDR 8X InfiniBand Link Layer Core
- 80 Gbit/second in ASICs
- 128 bit parallel interfaces
- 1X, 4X, 8X operation
- Link initialization and training
- Link layer flow control
- CRC generation and checking
- Protocol error and packet length checking
- Programmable Flow Control Period
- Dynamic Flow Control Mechanism
- Available for 1,4 & 8 Virtual lanes.
- Supports Xilinx, Altera and ASIC SerDes.
- Very low latency
- Fully portable, FPGA and ASIC compatible.
- IBA Rev 1.2 compatible
- Supports Altera Straitx2GX-3 and Xilinx Virtex5FXT when available
- 250MHz/500MHz clock
Technical Specifications
Availability
Now