Image Signal Processor IP enabling high performance real-time image processing

Overview

Key Features

• Baseline ISP Features
  • Support DVP Input Interface
  • Support 8-16 Bit Bayer RAW and ITU-R BT.601 & 656 Video Interface
  • Test Pattern Generator (TPG)
  • Black Level Measurement and Compensation (BLS)
  • Sensor Linear Correction
  • Defect Pixel Cluster Correction (DPCC)
  • Green Equalization
  • Lens Shading Correction (De-Vignetting)
  • Digital Gain
  • 2 Stage Adaptive Noise Filter
  • Enhanced Color Interpolation (Demosaic)
  • Chromatic Aberration Correction (CAC)
  • Color Correction Matrix (CCM)
  • Gamma Correction
  • Auto Focus Measurement (AF)
  • Auto White Balancing (AWB)
  • Auto Exposure Measurement (AE)
  • Histogram Calculation
  • Anti-flicker
  • Cropping of the Output Picture
  • Color Processing (Contrast, Saturation, Brightness, Hue) (CPROC)
  • Sharpening/Blurring Filter
  • Flash Light Control &Mechanical Shutter Control
  • Color Space Conversion (CSM)
• Advanced Features
  • Wide Dynamic Range Tone Mapping (WDR)
  • Multi-exposure HDR (Native/build in HDR, Compand output)
  • Multi-exposure HDR (DOL/Stagger, Stagger output)
  • Advanced 2DNR to Remove Spatial Noise
  • ISP8000 Support Advanced 2DNR-XL
  • 3DNR to Remove Temporal Noise
  • ISP8000 Support Advanced 3DNR-XL
  • Enhanced Chroma Noise Reduction (CNR)
  • Video Stabilization Support (VSM)
• Image Signal Processor Advantages
  • Ease of Integration, Very Low CPU loading, typical below 1 MIPS per frame / second
  • Ultra short capture delay (hard wired, separate preview & proc. path)
  • RAW data can be stored in memory for pre/post processing
  • Resolution scalable architecture (2MP, 4MP, 5MP, 8MP, 12MP, 18MP, 24MP, 36MP and up to 64MP)
  • Silicon proven design
  • High throughput rate up to 800 mega pixel/second (e.g. 8MP at 100fps)
  • FPGA platform available for pre-silicon software development
• Optional Added-On
  • Dual-ISP with Shared Memory Pool (SMP)
  • Multi-Context management to support two sensors within one ISP Core (MCM)
  • Tile mechanism for 8K resolution
  • RGB-IR 4x4 pattern
  • Configurable 10/12bit YUV output
  • RCCB and RCCC type sensor
  • PDAF Sensor
  • Function safety machanism, ASIL-B, ISO26262 certification
• Specific Output interface and Channels for ISP8000L/ISP8000
  • Main Digital Zoom (Main-Path Scaling) & Continuous Resize Support (MP)
  • Self-Digital Zoom, output path-1(SP-1)
  • Self-Digital Zoom, output path-2(SP-2)
  • Format Conversion Between YCBCr 4:2:2, 4:2:0, RGB Formats, Planar and Semi-Planar Storage Format for YCBCr
  • DMA Read Path to Feed Pipeline with Data from Memory
  • FLEXA API based stream interface to external blocks

Technical Specifications