IEEE1149.1-2001 JTAG access port

Overview

The Beyond TAP Controller is a fully IEEE 1149.1-2001 compatible JTAG Test Access Port (TAP) Controller. It is used for development and debugging purposes like Boundary Scan, Memory BIST. The Beyond TAP controller is an interface between the Boundary Scan / Memory BIST / Beyond Debug Interface Controller (which connects to the Beyond processor(s) and Beyond peripheral interface cores) and external debugger / emulator testing device.

Key Features

IEEE 1149.1-2001 compatible JTAG interface (TRST, TCK, TMS, TDI and TDO) to the external debugger / emulator testing device
Supported instructions:
- All mandatory public instructions (BYPASS, SAMPLE/PRELOAD and EXTEST)
- Optional public instruction (IDCODE)
- Private instructions (DEBUG and MBIST)
Supported scan chain registers:
- Internal Bypass register
- Internal ID register
- External Boundary Scan register
- External Debug Interface register
- External Memory BIST register

Benefits

Small: highly optimized, configurable Verilog RTL
Easy: fully documented, functional examples included
Safe: proven in volume production silicon
Flexible: fully configurable RTL
Standard: fully IEEE1149.1-2001 compatible

Block Diagram

Applications

Boundary Scan testing
Internal memory testing with Memory BIST
Software uploading and debugging with Beyond Debug Interface Controller
Beyond peripheral interface cores initialization with Beyond Debug Interface Controller

Deliverables

Soft core RTL in Verilog
Test bench in Verilog
Documentation
Engineering support

Technical Specifications

Foundry, Node

Process independent

Maturity

In volume production silicon

Availability

Now

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