The CT25205 Digital IP core provides the PMA, PCS, and PLCA Reconciliation Sublayer building blocks of a standard IEEE 802.3cg® 10BASE-T1S Ethernet Physical Layer.
The RTL code is written in plain Verilog 2005 HDL, and it is fully synthesizable on standard cells and FPGA systems. It works in conjunction with any standard IEEE CSMA/CD Clause 4 Ethernet MAC using MII.
The integrated PLCA RS allows existing MAC devices that do not support the new PLCA MII extensions to take advantage of the PLCA advanced features. On the other end, the PMA connects to a standard OPEN Alliance 10BASE-T1S PMD Interface.
The CT25205 can be used in conjunction to other analog and digital blocks like (a) the CT25203 to implement a complete physical layer ethernet device, (b) the CT25208 to implement a digital MACPHY and (c) the CT25203, the CT25208 and the CT25209 to implement a complete OPEN Alliance MACPHY.
