The CMS0005 802.16 Channel Codec provides all of the functionality necessary to implement the back end data processing in an 802.16a WirelessMAN-OFDM Phy Layer device. Its design has been carefully constructed to provide excellent FPGA performance without compromising the ASIC implementation in terms of area or speed.
A description of the processing steps follows:
Randomiser. This block implements the 802.16 randomisation function 1+x14+x15. In addition it controls the burst profiling of the transmitter and zero-tail byte insertion specified by 802.16a. The burst profile can be any of the QAM orders and coding rates that are specified by 802.16a. The burst profile control requires the MAC software to write the specifications of the bursts into a FIFO within the register bank. Once the randomiser has the burst profile it will request data from the MAC at a rate determined by the front end of the modulator.
Reed-Solomon Encoder. This block will generate Reed Solomon packets based on the burst profile supplied by the randomiser.
Transmit Byte Order Processing. 802.16a specifies that the Reed-Solomon parity bytes be transmitted before the payload in order that the zero tail-byte inserted by the scrambler is kept at the end of the packet. This block handles this reversal in addition to converting the byte stream to the bit stream required by the Convolutional Encoder.
Convolutional Encoder. This block performs the zero-terminating convolutional encoding as specified by 802.16a.
Interleaver, Mapper. 802.16a specifies a block interleaver in a two-step permutation. These blocks perform that interleaving in addition to the QAM constellation mapping. It outputs I/Q QAM symbols to the modulator.
Demapper, De-interleaver. These blocks perform the soft decision demapping of the I/Q samples from the demodulator. In addition, they perform the de-puncturing function required by the Viterbi Decoder.
Viterbi Decoder. This block performs the Viterbi Decoding function with zero-flush as specified by 802.16a. For further details on this block see the separate data sheet for CMS0002, the Commsonic Viterbi Decoder.
Receive Byte Order Processing & Burst Profile Processing. This block takes the bit-stream input from the Viterbi decoder and converts it to a byte stream before reversing the parity/payload order in order that the data is formatted correctly for receipt by the Reed-Solomon decoder. In addition, it manages the burst profiles used by the receiver. This includes extraction of the Frame Control Header (FCH) from the first OFDM symbol of a downstream frame and setting the parameters for the remainder of the receive chain to match the required QAM order and code rate. Settings for the burst following the FCH symbol are managed automatically; all other burst profile settings are programmed by software.
Reed-Solomon Decoder. This block will perform Reed-Solomon decoding and error correction of the received packets. For full details of this block see the Commsonic data sheet for the CMS0003, the Commsonic Reed Solomon Decoder.
De-Randomiser. This block applies the same randomising polynomial as the randomiser in order to recover the received data. In addition, it removes the zero tail-byte that was applied for the convolutional encoding/decoding. It outputs the received data stream delineated using the sync pulse.
Register Bank. The register bank provides a simple 32-bit interface for reading and writing registers within the FEC block. Full details of the registers within the FEC core are contained within the full data sheet.
