IEEE 802.16 WiMAX High Speed 8 State Turbo Decoder

Overview

This is a high speed IEEE 802.16 WiMAX 8 state duobinary turbo decoder with four parallel MAP decoders.

Key Features

  • 8 state IEEE 802.16 WiMAX compatible turbo decoder
  • Rate 1/2 or 1/3
  • 40 to 4864 bit interleaver
  • Up to 192 MHz internal clock
  • Up to 137 Mbit/s with 5 decoder iterations
  • 6-bit signed magnitude input data
  • 4 parallel MAP decoders
  • Optional log-MAP or max-log-MAP constituent decoder algorithms
  • Up to 32 iterations in 1/2 iteration steps
  • Optional power efficient early stopping
  • Optional extrinsic information scaling and limiting
  • Estimated channel error output
  • Free simulation software
  • Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6, Spartan 6 and 7-Series FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
  • Available as VHDL core for ASICs

Block Diagram

IEEE 802.16 WiMAX High Speed 8 State Turbo Decoder Block Diagram

Deliverables

  • All Licenses
    • EDIF Core
    • VHDL Simulation Core
    • Test vector generation software
  • VHDL ASIC License
    • VHDL Core

Technical Specifications

Availability
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Semiconductor IP