IEEE 802.11 n/ac/ax LDPC Encoder

Overview

The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures.
The ntLDPC_80211 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity.
The ntLDPC_80211 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utili-zation trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards.

Key Features

Encoder and decoder, support all IEEE 802.11 n/ac/ax de-fined block lengths (648, 1296, 1944) and code rates (1/2, 2/3, 3/4 and 5/6).
27-Bit or 81-Bit encoder input/output interface wrappers, supporting AXI4 Lite bus protocol.
Soft input decoder interface wrapper with 4(S4.0), 5(S5.0, S5.1) or 6(S6.0, S6.1, S6.2) bit LLRs support and 27*LLR or 81*LLR parallelism.
Automatic scaling of internal fixed point precision according to selected input fixed point precision.
Flexible generic decoder architecture with various combina-tions of parallelism options providing any desired application trade-off between area, performance and throughput rates.
Maximum internal parallelism level of 81 parallel LLRs pro-cessing for high throughput applications.
Programmable number of algorithmic iterations.
Programmable Early Termination feature, with layered par-ity check criterion, for substantial throughput rate increase, without any measurable performance loss.
Probe outputs returning the number of actual performed decoding iterations per frame for quality statistics extraction.
Generic selection of multiple encoder/decoder instances under the same top level IO interface for seamless through-put increase.
Peak data rate > 4Gbps, measured on Xilinx RFSoC FPGA, with ~10% device utilization. Higher rates achievable for FPGA or ASIC technologies.
Synchronous single clock design.
Silicon proven in ASIC and Xilinx FPGA implementation technologies.

Block Diagram

Applications

IEEE 802.11 n/ac/ax Wi-Fi 4, 5 or 6 standard compliant cases.
Custom state-of-the-art systems for efficient high throughput FEC protection in both wire-line or wireless types of applications.

Deliverables

Fully commented synthesizable VHDL source code or FPGA netlist.
VHDL test bench and example configuration files.
Matlab model.
Comprehensive technical documentation.
Technical support.

Technical Specifications

Foundry, Node

TSMC 28nm

Maturity

Silicon Proven

Availability

Now

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