IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI I3C IP > I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus

I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus

Overview

The DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improved Inter Integrated Circuit specification.

The I3C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I3C devices as well as legacy I2C Slave devices.

The DB-I3C-MS-APB is a I3C Controller supporting I3C SDR / Broadcast / Direct Messages, Legacy I2C Message, and I3C HDR Mode (optionally).

In an ASIC / ASSP / FPGA integrated circuit, typically, the microprocessor is an ARM or RISC-V processor, but can be any embedded processor. Figure 1 depicts the system view of the DB-I3C-MS-APB Controller IP Core embedded within an integrated circuit device with its Microprocessor Configuration.

Key Features

  • Master / Slave MIPI I3C Controller
  • Supports following I3C bus speeds:
    • Single Data Rate (SDR) - up to 12.5 MHz
    • High Data Rate (HDR) (Optional)
  • I3C Communications Support:
    • I3C SDR / Broadcast / Direct Messages
    • Legacy I2C Message
    • I3C HDR Mode (optional)
  • I3C compliant features:
    • Dynamic Addressing Assignment
    • Secondary Master Function
    • In-Band Interrupt
    • Hot-Join Mechanism
    • Synchronous/ Asynchronous Timing Stamping
    • I3C Characteristics Registers
    • Common Command Codes (CCCs)
  • Parameterized FIFO memory for off-loading the I3C transfers from the processor:
    • Targets embedded processors with the I3C Controller independently controlling the I3C Message Transmit/Receive with bytes of informationbuffered to and from a FIFO.
    • Dual Clock FIFO, decoupling APB bus & I3C clock domains
    • FIFO parameterizable in depth and width
  • System-level features & integration capabilities:
    • CPU Interface to Control / Status Registers & parameterized FIFO with support for APB / AHB / AXI / AXI-lite / Avalon SoC Interconnectfabrics
    • Internal Interrupt Controller (Interface to embedded processor)
  • Optional system-level features & integration capabilities:
    • DMA transfer between the I3C Bus & Memory (SDRAM / SRAM / FLASH)
  • Compliance with I3C, I2C, and AMBA specifications:
    • MIPI Alliance – Specification for I3C – Improved Inter Integrated Circuit, Version 1.0, 23 December 2016 (doc “mipi_I3C_specification_v1-0”)
    • Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and UM10204 Rev 6 – 4 April 2014
    • Compliance with AMBA Specification – APB

Block Diagram

I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus Block Diagram

Deliverables

  • Verilog RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Technical Specifications

Foundry, Node
Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC, GLOBALFOUNDRIES, Renesas, Samsung, HHGrace
Maturity
Successful in Customer Implementations
Availability
Immediately
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