DTI I2C Controller provides the logic consistent with NXP I2C specification to support the communication of low-speed integrated circuits through I2C bus.
The IP facilitates software controllable by application processor through industry-standard AMBA interface. The bus interface is flexible and easily integrated into APB, AHB or AXI system bus.
I2C Controller & PHY
Overview
Key Features
- + Support Master only and Slave only and Master & Slave operation
- + 5 speed modes: SS, FS, FS+, HS, UHS (maximum: 5Mbps)
- + Singled or combined message protocol
- + 7-bit or 10-bit addressing
- + Clock synchronization and Slave clock stretching
- + Software interface consistent with AMBA Advanced Peripheral Bus (APB), configurable bus width 8/16/32
- + Input spike suppression and Interrupt interface
- + DMA hand-shaking interface and Programmable FIFO watermarks
- + Bus arbitration, General call address, Bus clear operation, Read device ID
- + Programmable timing parameters, including (tLOW), (tHIGH), (tHD;STA), (tSU;STA), (tHD;DAT), (tSU,STO), (tBUF), and (tSP)
Benefits
- Compliant with the following specifications:
- I2C Bus Specification
- AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
Applications
- Communications, Data Processing, Industrial, Automotive
Deliverables
- Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- Synthesis and STA scripts
- User guide documents
- SV/UVM Verification suite with BFM
Technical Specifications
Maturity
Pre Silicon
Availability
Yes
Related IPs
- I2C Controller IP – Master, Parameterized FIFO, APB Bus
- I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
- I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
- I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
- I2C Controller IP – Master, Parameterized FIFO, AHB Bus
- I2C Controller IP – Master, Parameterized FIFO, AXI Bus