The Integretek HyperLink Core allows the creation of a user defined system which can communicate with remote TI Cx66 DSP devices via a high speed SERDES interface. The core provides a high-speed communication interface that extends the AXI interface over a serial connection. The HyperLink FPGA core leverages the same proven HyperLink IP used within the TI multi-core DSPs. The core is available with either an industry standard AXI interface or an easy to use DMA interface.
HyperLink High Speed DSP Interface Core
Overview
Key Features
- Up to 25Gbps transfer rate (4 lane)
- Point-to-point connection
- Link self-initializes
- Supports multiple outstanding read, write and interrupt transactions
- Simple packet-based transfer protocol for memory mapped access
- AXI4 Interface Complies with AMBA AXI Protocol V2.0
- 64 user defined interrupt inputs, level and pulse sensitive
- AXI4 Slave (transmit to DSP and Control Register access)
- AXI4 Master (receive from DSP)
- Optional DMA interface
Block Diagram
Technical Specifications
Related IPs
- High Speed Data Bus (HSDB) IP Core
- 400G/800G High Speed Ethernet Controller MAC/PCS/FEC
- 10G to 400G High Speed Channelized Ethernet Controller MAC/PCS/FEC
- 1G to 200G High Speed Channelized Ethernet Controller MAC/PCS/FEC
- High speed low latency AES-GCM pipeline, 100Gbps
- 200G/400G High Speed Ethernet Controller MAC/PCS/FEC