HMC Synthesizable Transactor provides a smart way to verify the HMC component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's HMC Synthesizable Transactor is fully compliant with standard HMC Specification and provides the following features. Better than Denali Memory Models.
HMC Synthesizable Transactor
Overview
Key Features
- Supports 100% of HMC protocol standard 1.0, 2.0 and 2.1
- Supports all the HMC commands as per the specs
- Supports 2,4 and 8 link configuration
- Supports for half width(8-lanes) and full width(16-lanes)
- Supports 16, 32, 48, 64, 80, 96, 112, 128 and 256 byte request
- Supports 12.5 Gb/s, 15 Gb/s, 25 Gb/s, 28 Gb/s, or 30 Gb/s serdes I/O interface
- Supports packet-based data/command interface
- Supports poison packets handling
- Supports scrambler and descrambler
- Supports training sequence
- Supports lane reversal and polarity inversion
- Supports all block size setting
- Supports flow control
- Supports link retraining
- Supports packet retry
- Checks for following:
- Check-points include power up,initialization and power off rules
- State based rules, active command rules
- Read/Write command rules etc
- All timing violations
- Supports various types of error injection support
- Supports write data mask and data strobe features
- Supports 4GB/8GB configuration
- Supports internal ECC data correction
- Supports error detection (cyclic redundancy check [CRC]) for packets with automatic retry
- Supports power management supported per link
- Supports built-in self-test (BIST)
- Supports JTAG interface (IEEE 1149.1-2001, 1149.6)
- Supports I2C interface up to 1 MHz
- Supports SPI master interface
- Notifies the test bench of significant events such as transactions, warnings,timing and protocol violations
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the HMC testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes