The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement:
* SpaceFibre controller (GRSPFI)
* WizardLink controller (GRWIZL)
* ...or both (GRHSSL)
Thanks to the DMA engine, receive and transmit data are autonomously transferred between the serial link and the on-chip bus, which in turn can be either AMBA AHB or AXI.
Highly configurable high-speed serial link controller
Overview
Key Features
- SpaceFibre codec designed according to the SpaceFibre specification ECSS-E-ST-50-11C, single-lane implementation
- WizardLink codec designed to interface with Texas Instrument TLK2711 transceiver
- The IP can inter-operate with off-chip SerDes devices or with FPGA/ASIC hard macros
- Optional 8b10b encoding
- Support for wide (36/40) or narrow (16/20) SerDes interfaces
- Configurable number of DMA channels
- Optional SpaceFibre RMAP support
- Optional fault tolerant features
- Support for both big-endian and little-endian systems
Block Diagram
Technical Specifications
Related IPs
- Synchronous Data Link Controller
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- TDM-Rx-Pro: Configurable Multi-channel Serial Audio Receiver
- TDM-Tx-Pro: Configurable Multi-channel Serial Audio Transmitter
- TDM-Pro : Configurable Multi-Channel Serial Audio Transceiver
- MIPI HSI Controller - (High-Speed Synchronous Serial Interface)