High-Stable Oscillator - TSMC 40nm(CLN40ULP) / UMC 55nm(LP)

Overview

The High Stability Oscillators generate 150MHz - 160MHz output frequency with an accuracy of +/-2% or +/-3% or +/-5%.
The oscillators need trimming, and stable power supply.
Have mass production results at each technology node.

Key Features

High accuracy +/-2%, +/-3%, +/-5% at Tj = -40C to +125C.
The frequency can be adjusted from 150MHz to 160MHz.
Reference clock is not required.
Need to use trimming.
The +/-2% version requires both a stable IO voltage and a core voltage.
The +/-3% version requires only a stable core voltage at TSMC 40nm (CLN40ULP).
The +/-5% version requires only a stable core voltage at UMC 55nm (LP).
As an option, we can provide the eFuse-wrapper for trimming. In this case, the trimming resource is fixed to TSMC/UMC eFuse.

Applications

General Purpose

Deliverables

GDSII
CDL netlist
Verilog model
Synopsys synthesis model
LEF
User Guidelines

Technical Specifications

Foundry, Node

TSMC 40nm (CLN40ULP), UMC 55nm LP

Maturity

In Production

TSMC

In Production: 40nm LP , 55nm LP , 110nm G
Silicon Proven: 40nm LP , 55nm LP , 110nm G

UMC

In Production: 55nm
Silicon Proven: 55nm

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