IP Catalog > Analog IP > PLL IP > General Purpose PLL IP > High Speed PLL

High Speed PLL

Overview

This PLL IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By proper configurations to different values according to different FREF, CLK will be locked at the multiples of input frequency. CLKO is CLK divided by DP.
 

The output clock has excellent jitter performance, and can be used as high speed clock generator in SoCs and provide clock for high accuracy ADC converters.

Key Features

  • Silicon proven in 22, 28, 40, 55, 65, 110, 130, 180nm from SMIC, HHgrace, GlobalFoundries and Samsung.
  • Support integer mode, Fraction mode and Spread-Spectrum mode
  • Input reference range:10MHz~100MHz
  • VCO frequency range:
    •   800~3200MHz                        
  • Core Area:0.0678 mm^2  
  • Output VCO clock period jitter peak –peak value :+/-2.5% of output period
  • Internal Post-divider to provide wide range output frequency
  • Power consumption, current on AVDD:
    •   1mA typ@FVCO=1GHz,                       
    •   4mA typ@FVCO=3GHz

Block Diagram

High Speed PLL Block Diagram

Technical Specifications

Availability
GDS Ready
SMIC
Pre-Silicon: 28nm HK , 40nm LL , 55nm G , 65nm LL , 110nm G , 130nm LV
Samsung
Pre-Silicon: 28nm LPP , 65nm LP
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