The H264-HP-E core is an advanced and self-contained ITU-T H.264 High profiles hardware encoder. This core is available in Intra-only [IDR], Light Motion Estimation [LME] and Full Motion Estimation [FME] prediction engine configurations. It supports real time encoding of both single and multiple 4:2:0 and 4:2:2 video streams, in 8-, 10- or 12-bit per component color depth, up to Profile Level 5.2. Encoding in the Constrained Baseline and Main profiles is also supported. The H264-HP-E is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
The encoder accepts the uncompressed video data in planar, interleaved, or macroblock scan format. It outputs standalone, standard compliant, Annex B NAL byte stream. No post processing on the output stream, other than (for example) stroring, muxing or transmitting, is required. The output NAL byte stream can be decoded, as is, by any ITU-T H.264 compliant decoder that satisfies the Level requirements of the stream and conforms to the corresponding ITU-T H.264 profile.The H264-HP-E requires minimal host intervention as it only needs to be programmed once per video sequence. Once programmed, it can encode an arbitrary number of video frames without needing any CPU, GPU, or other type of support by the host system.
The H264-HP-E core implements a simple and flexible, requests based, external memory interface with independent read and write data paths. This makes the H264-HP-E independent of memory type, supporting for example operation with SRAM, SDRAM, DDR, DDR2 and DDR3 types of memory. The encoder is designed to be tolerant to memory delays and latencies, which may be present on shared memory system architectures.
The H264-HP-E core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the H264-HP-E is a reliable and easy-to-use and integrate IP.
