The SiFive Performance™ P500 application processor features a thirteen-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GBC ISA. The Performance P500 scales up to four-core complex configurations while delivering 30% higher performance in less than half the area of a comparable Arm® Cortex®-A75.
High performance three-issue, out-of-order RISC-V vector application processor
Overview
Key Features
- Breakthrough RISC-V performance
- Multi-core, multi-cluster processor configuration, up to 8 cores
- 3x Performance per mm2 compared to Arm® Cortex®-A75
- Performance >8.6 SpecINT2k6/GHz, higher single thread performance than Arm Cortex-A75
- P500 Core Architectural Features
- 64-bit RISC-V core with Sv39/Sv48 Virtual Memory Support
- Three Issue, out-of-order pipeline tuned for scalable performance
- Private L2 Caches and Streaming Prefetcher for improved memory performance
- SECDED ECC with Error Reporting
- Enabling next generation applications
- Cache stashing to L3 for tightly coupled accelerators
Block Diagram
Deliverables
- RTL Evaluation
- Test Bench RTL
- Software Development Kit
- FPGA Bitstream
- Documentation
Technical Specifications
Availability
Now
Related IPs
- High Performance 64-bit RISC-V Multi-Core Application Processor
- Highest performance four-issue, out-of-order RISC-V vector application processors
- High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP
- Ultra High Performance 32-bit RISC-V Embedded Processor
- Ultra High Performance 64-bit RISC-V Embedded Processor
- High performance 32-bit RISC-V Processor