High-Performance Low-Power 32-bit RISC core
Overview
The C310 is a member of theC*Core TM High-Performance Low-Power 32-bit RISC core family. It has been designed for high-performance and cost-sensitive embedded applications, with particular emphasis on reduced system power consumption, making it suitable for battery-operated, portable products. The C310 extends the C210 instruction set and functionality by integrating an integer array multiplier, branch prediction and folding, improved pipelining of load and store operations, and a deeper instruction buffer to improve memory bandwidth utilization.
Key Features
- Low power RISC core
- 32-bit load/store architecture
- Highly optimized pipeline
- Single-cycle 32x16 multiplier
- Fixed-length 16-bit instructions
- Mostly single-cycle execution
- Two-cycle branch execution
- 16 32-bit general purpose registers
- 13 32-bit control registers
- C*Bus MLB bus architecture
- Support byte/halfword/word access
- Optional AMBA wrapper
- Fast interrupt support
- 16 32-bit alternate registers for fast context
- switching
- Vectored/auto-vectored interrupts
- 128 interrupt/exception vectors
- Debug support via JTAG-based OnCE Design
Technical Specifications
Foundry, Node
SMIC 0.18ìm (WCS, 1.62V, 125°C)
Availability
now
SMIC
Pre-Silicon:
180nm
G