HDMI - Display Port Combo PHY IP, Silicon Proven in TSMC 28HPC+

Overview

The DisPlay Port/HDMI/DVI Receiver is a high performance combo PHY with Display Port Receiver and HDMI Receiver. In DisPlay Port mode, the receiver is VESA DP1.1a, DP1.2 and eDisPlay Port compliant with four main lanes and an auxiliary channel. In addition to the standard DP1.1a HBR (2.7Gbps) and RBR (1.62Gbps) data rates, it can also support turbo mode (3.24Gbps) and HBRII (5.4Gbps) of DP1.2 standard. The IP does not support the optional FASTAUX and postcursor2 requirements of the DP1.2 standard. To facilitate lower test cost and improve test coverage, AUX channel include some testability features. In HDMI mode, the IP is HDMI 1.4b compliant. It can be customized process nodes from multiple foundries..

Key Features

  • Compliant with HDMI 1.4b & Display Port version 1.4 specification.
  • Input clock 135MHz for Display Port.
  • Supports upto HBRII (5.4Gbps/Ch) of DP 1.2 standard, 3D 1080p @60Hz.
  • Up to 21.6Gbps BitRate (4 X 5.4Gbps/Channel) in DP mode, 10.2Gbps (3 X 3.4Gbps/Channel) in HDMI mode.
  • 3.3V+5%, 1.8V+5% (Analog Supply), 1.0V+5% Analog Supply
  • Power On Consumption: Under NDA (Typ Process, HBR2 Display Port), Under NDA (Typ Process, 3.4Gbps/Ch HDMI).
  • At Speed BIST (Loop Back Test) incorporated.
  • Silicon Proven in TSMC 28nm HPC+

Applications

  • Digital TV
  • Tablets
  • Mobile phones
  • Digital camera
  • Camcorders
  • Soundbars
  • Audio/Video Receivers
  • DVD players
  • Recorders
  • Streaming-media players
  • Set-top boxes
  • Home theater systems
  • Game consoles

Deliverables

  • Detailed specification with All log files and signoff checklist
  • Integration Guidelines ( Interface details, layout guidelines, power requirements)
  • GDSII layout and Mapping file with LEF Abstract (Top level pin details, blockages and Boundary details)
  • LVS compatible netlist for the LVS clean

Technical Specifications

Foundry, Node
TSMC 28HPC+
Maturity
In Production
Availability
Immediate
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Semiconductor IP