The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 specification.
Forward Error Correction is required to ensure glitch-free operation in Fix Rate Lane (FRL) mode, a packet mode introduced in HDMI 2.1. FRL allows for the use of Display Stream Compression (DSC) bitstream transport.
HDMI 2.1 Forward Error Correction (FEC) Transmitter
Overview
Key Features
- HDMI 2.1 compliant
- Reed-Solomon RS(255,251) FEC, 8-bit symbols
- Supports 3-lane and 4-lane operation
Block Diagram
Applications
- GPUs
- Desktops & laptops
- UHD TVs & set-top boxes
- Professional video equipment
Deliverables
- Encrypted RTL source code IP core
- Functional and structural coverage reports
- Comprehensive integration guide
Technical Specifications
Related IPs
- HDMI 2.1 Forward Error Correction (FEC) Receiver
- ASIL-B Ready ISO 26262 Certified VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- IEEE 802.3bj Reed-Solomon Forward Error Correction