HDMI 2.1 eARC TX PHY in TSMC (16nm, 12nm)

Overview

The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify designs for various HDMI-based
applications. The silicon-proven HDMI 2.1 IP provides quality digital video and audio transmission with up to 48Gbps aggregate bandwidth for uncompressed 8K resolution at 60Hz refresh rate. It supports the required features of HDMI
2.1 including dynamic HDR and enhanced audio return channel (eARC) and more, ensuring higher video quality and most advanced audio formats. The IP also supports latest HDMI 2.1a addition for Source based tone mapping.
The complete power- and area-optimized HDMI 2.1 RX IP solution encompasses a suite of configurable digital controllers, high-speed, mixed-signal PHYs, PLL, verification IP, High-bandwidth Digital Content Protection (HDCP) embedded security modules (ESMs), Display Stream
Compression (DSC) IP, all pre-integrated and shipped with a reference system. Having all necessary design blocks for the HDMI subsystem enables system- on-chip (SoC) designers to lower integration risk and accelerate time-to-market.

Key Features

  • Quad-pixel interface allows up to 48Gbps bandwidth data for uncompressed 8K resolution with 60Hz refresh rate
  • Fixed-rate stream with 16b18b decoding and de-scrambling
  • Supports latest object-based audio formats with 1536kHz sample rate and up to 32 channels
  • Dynamic metadata packets reception
  • Auto low-latency mode/variable refresh rate
  • Optional HDCP decryption engine compliant with HDCP 2.3, 1.4 specifications
  • I2C target access for HDCP authentication
  • Supports true-color (24-bit) and deep-color modes (30, 36 or 48-bit)
  • Supports all CTA-861-G video formats up to 8K and 10K
  • Digital audio interface includes four I2S, four S/PDIF, parallel audio output and audio sample output (ASO)
  • Flexible power management modes (implements power gating)
  • Registers access by Arm AMBA 3 APB
  • Integrated CEC 2.0 hardware engine
  • Software drivers (ported into Linux)

Benefits

  • HDMI 2.1 RX IP solution includes PHYs, controllers, HDCP embedded security modules, and verification IP
  • Compliant with the HDMI 2.1a, 2.0b, 1.4b and HDCP 2.3, 1.4 and VESA DSC 1.2a specifications
  • Support for key HDMI 2.1a features such as fixed-rate link capable of 48Gbps aggregated bandwidth, enhanced metadata packets including dynamic HDR, eARC, auto low-latency mode and variable refresh rate.
  • Optimized for low power and small area.
  • Timing hardened blocks simplify placement and design closure
  • Configurable controller architecture optimized for power, performance, and area

Applications

  • Digital television
  • PC monitors and projectors
  • Home theater system, audio/video receivers and sound bars
  • AR/VR systems
  • In Vehicle Infotainment (IVI)

Deliverables

  • Databook, user guide, installation guide and release notes
  • Verilog RTL source code
  • Simulation testbench
  • VCS, Design Compiler, SpyGlass and Formality scripts

Technical Specifications

Foundry, Node
TSMC 16nm, 12nm - FFC
Maturity
Available on request
Availability
Available
TSMC
Pre-Silicon: 12nm , 16nm
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Semiconductor IP