HDMI 2.0 TX PHY 6Gbps in TSMC (28nm, 16nm, 12nm)

Overview

The Synopsys HDMI Transmitter (TX) IP solutions are compliant with the HDMI
2.0 and 1.4 specifications, and provide the necessary logic to implement and verify designs for various consumer electronic applications.
The power- and area-optimized IP solutions are silicon-proven and include a suite of configurable digital controllers and high-speed, mixed-signal PHY IP. Shipping in volume and having gone through extensive in-house and third-party interoperability testing, the IP solutions enable system-on-chip (SoC) designers to lower integration risk and accelerate time-to-market. The IP solutions are HDMI 2.0 and HDCP 2.3 certified with embedded security modules, ensuring the highest content protection over the HDMI 2.0 interface or ultra-high- definition multimedia SoCs.
Synopsys’ complete HDMI IP solution consists of digital controllers, High- Bandwidth Digital Content (HDCP) embedded security modules (ESMs), PHYs and verification IP as well as IP Prototyping Kits with associated software and drivers.

Key Features

Compliant with the latest HDMI 2.0/1.4 and DVI specifications
Four levels of pre-emphasis for long cable support and clean signals
Hot plug detect allows changing of cables and components without switching off the entire system
Support for 5V I/O on all nodes (down to 28-nm nodes)
Aggressive ESD protection
Input clock from 25 MHz to 600 MHz range
Aggregate bandwidth of 18.0 Gbps to support 4K x 2K resolution at 60 Hz frame rate and 8-bit per color for a flickerless ultra high-definition experience
Integrated test features including scope, BIST and loopbacks
Optimized pin count, small area and low power ensure low BOM cost

Benefits

Silicon-proven High-Definition Multimedia Interface (HDMI) TX IP includes controllers, HDCP ESMs, PHYs, verification IP, and IP Prototyping Kits
HDMI 2.0 and HDCP 2.3 certified
Support for key HDMI 2.0 features such as 4K x 2K resolution at 60 Hz frame rate, YCbCr 4:2:0 pixel encoding format, TMDS scrambling, High Dynamic Range (HDR), CEC 2.0 and 18.0 Gbps aggregate bandwidth
Fully compliant with HDMI 2.0/1.4 specifications with all required features
Optimized for low power and small area
Timing hardened blocks enable simplified placement and design closure
High-performance TX PHY IP enables long cable lengths
Configurable controller architecture optimized for power, performance, and area

Applications

Blu-ray/DVD players or recorders
Streaming-media players
Set-top boxes
Audio/video receivers
Game consoles
Tablets and mobile phones
Digital camera and camcorders

Deliverables

Databook
Application notes
Assembly guidelines
Design files kit: Behavioral model; .LEF file; .LIB file; GDSII layout database

Technical Specifications

Foundry, Node

TSMC 28nm, 16nm, 12nm - HPM, HPC, FFC

Maturity

Available on request

Availability

Available

TSMC

Pre-Silicon: 12nm , 16nm , 28nm

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