HDCP Encryption-Decryption Engine

Overview

The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption Decryption Engine IP core implements the HDCP 1.3/2.3 digital stream cipher for both encryption and decryption operations. When used in combination with the Trilinear HDCP Authentication Software Stack running on a local processor, this IP core provides a complete, real-time solution for HDCP 1.x or HDCP 2.x protection of a digital link.

Data in

Streaming interface using parallel data format for processing multiple symbols per clock cycle.

Data out

Low-latency streaming interface that parallels the input interface, providing consistent latency in both encrypted and plain text modes.

Host

32-bit AMBA Peripheral Bus (APB) 4 interface for configuration information and control.

Key Features

Real-time encryption/decryption
8k compression available for select applications
Low gate count and low latency implementation
Supports HDCP 1.3 and 1.4
- R0, M0 hardware calculations
- Optional hardware key interface for master key calculations
- Host-free operation after initial authentication
Supports HDCP 2.2/2.3
- Hardware calculations for dkey0, dkey1, dkey2, and Ekh values
- AES-128-compliant
Fully integrated authentication management
Source, sink, and repeater support
Typical performance is 400 MHz in 12 nm
Implementation resource usages:
- Xlinx Kintex-7: 15K LUT, 6K FLOP
- ASIC: 150K gates

Block Diagram

Deliverables

HDL source files for function design
Fully functional models for block-level and top-level testing, including over 120+ tests in the user-level environment
Functional specification
Timing constraints summary document
Generic SRAM simulation models
C Reference Driver

Technical Specifications

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