The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption-Decryption Engine IP core allows system designers to accelerate time to market and reduce design risks with an HDCP standards-compliant encryption and decryption engine. HDCP is a technology developed by Intel Corporation designed to strongly protect in real-time high-value streamed content, such as HD and UHD feature films, being sent over a data link.
Our HDCP Encryption-Decryption Engine IP core is compliant with the HDCP 1.3/2.3 specifications. When deployed with the Trilinear HDCP Authentication Software Stack running on a local processor, this IP core provides a complete, real-time solution for HDCP 1.x or HDCP 2.x protection of a digital link.
HDCP Encryption-Decryption Engine
Overview
Key Features
- Real-time encryption/decryption
- 8k compression available for select applications
- Low gate count and low latency implementation
- Supports HDCP 1.3 and 1.4
- R0, M0 hardware calculations
- Optional hardware key interface for master key calculations
- Host-free operation after initial authentication
- Supports HDCP 2.2/2.3
- Hardware calculations for dkey0, dkey1, dkey2, and Ekh values
- AES-128-compliant
- Fully integrated authentication management
- Source, sink, and repeater support
- Typical performance is 400 MHz in 12 nm
- Implementation resource usages:
- Xlinx Kintex-7: 15K LUT, 6K FLOP
- ASIC: 150K gates
Benefits
- Verification testing was completed using a bottom-to-top methodology. Testing is first performed at the module level and progresses up to system level. With the HDCP EncryptionDecryption Engine IP core, module-level testing consists of generating both randomized and corner case (boundary value) conditions.
- Trilinear Technologies delivers an extensive design database for the HDCP EncryptionDecryption Engine core. In addition to the synthesizable RTL IP core and extensive user level verification environment, the database includes all the files required to implement the design on multiple platforms, including FPGA and ASIC technologies. Reference software drivers and applications are included, along with associated documentation to reduce the amount of time for software development.
- Files and data include:
- Design Database
- HDL source files for function design
- Fully functional models for block-level and
- top-level testing, including over 120+ tests
- in the user-level environment
- Functional specification
- Timing constraints summary document
- Generic SRAM simulation models
- C Reference Driver
Block Diagram
Deliverables
- The HDCP Encryption-Decryption Engine IP core ships with a standards-compliant implementation of the HDCP Authentication protocol.
- The software provides hardware accelerated and software implementations of all of the encryption algorithms to implement a complete system.
- The stack has been designed to meet the requirements of the HDCP Authentication speeds on a reasonable 32-bit microcontroller.