Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM3 JEDEC standards
HBM3E Controller
Overview
Key Features
- One stop PHY & Controller solution with an average random efficiency of more than 85%
- Supports up to 8000 MT/s
- DFI 5.0 compatible interface to the memory controller
- Flexible PHY with programmable intelligent interface training sequences
- Flexible IEEE1500 interface to support memory vendor customizations
- Supports up to 32Gb density per die
- Supports up to 16H HBM3E DRAM stacks
- Supports major 2.5D/3D packaging technologies including support for interposer designs and interconnect and memory repairs
- Add-on features/engines for MPFE, RAS and Debug available upon request
- Add-on feature for generic 2.5D die-to-die data transport interconnect