HBM3 PHY V2 in TSMC (N5, N3E)

Overview

The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC, ASSP, and system-on-chip (SoC) applications requiring high-bandwidth HBM3 DRAM interfaces operating at up to 9600 Mbps. The synopsys HBM3 PHY offers superior power efficiency compared to any other off-chip memory interface and supports up to 4 active operating states enabling dynamic frequency scaling. To minimize area, the PHY utilizes an optimized micro bump array. Support for longer channel lengths allows more flexibility in the PHY placement on the SoC without impacting performance. The PHY provides a complete HBM3 interface solution when combined with Synopsys’ HBM3 Controller IP and HBM3 memory model VIP.
The configurable Synopsys HBM3 PHY is provided as a set of hard macrocells delivered as GDSII. These hard macrocells include integrated application- specific HBM3 I/Os required for HBM3 signaling. The design is optimized for high performance, low latency, low area, low power, and ease of integration.
The hard macrocells are easily assembled into a complete 1024-bit HBM3 PHY. The RTL-based PHY Utility Block (PUB) supports the GDSII-based PHY components and includes the PHY training circuitry, configurations registers
and BIST control. The HBM3 PHY includes a DFI 5.0-compatible interface to the memory controller, supporting DFI 1:1:2 and DFI 1:2:4 clock ratios. The design is compatible with both metal-insulator-metal (MIM) and non-MIM power decoupling strategies. Synopsys also offers a pre-hardened “drop-in” version of the Synopsys HBM3 PHY for customers that do not have significant custom requirements. For customers that require a custom hard Synopsys HBM3 PHY, Synopsys also offer PHY hardening design services.

Key Features

Low latency, small area, low power
Compatible with JEDEC standard HBM3 DRAMs
Data rates up to 9600 Mbps
8H, 12H and 16H HBM3 DRAM stacks supported
Support for fast switching between up to 4 frequencies
Product subcomponents designed to precisely control timing critical delay and skews
Controller DFI-compatible interface (DFI v5.0 Addendum 2)
Includes 1 phase-locked loop (PLL) per PHY and digital delay lines necessary to meet timing specifications
Separate transmit DQ and transmit DQS as well as transmit Row/Col and transmit CK delay lines
Includes separate receive DQS delay lines for both rising and falling edge of DQS
Supports 32 pseudo-channel HBM3 DRAM systems
Boot time impedance calibration
Programmable I/O drive strength matching the HBM3 DRAM
Delay line VT compensation
Time axis data eye training
PHY VREF can either be supplied externally through a bump or use an internal VREF generator that can provide a programmable VREF for use internal to the PHY
Physical implementation of the top-level HBM PHY hard macro is designed to be compatible with a face centered rectangular (FCR) micro bump pattern similar to the HBM3 micro bump pattern
Area optimized micro bump pattern for smaller PHY area
Enhanced power savings support that includes:
Arm® AMBA ® APB interface for configuration register access
Test data register (TDR) interface for configuration register access
Multiple test modes
At-speed loopback testing on both the address and data channels
Pre-hardened HBM PHYs are available in select process technologies
Services available for custom PHY hardening requirements
2.5D Interposer reference designs available

Benefits

Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
16 independent 64-bit memory channels
Pseudo-channel operation supported to enable up to 32 32-bit pseudo-channels with 1024 bit PHY
Supports up to 4 trained frequencies with <5us switching time
DFI 5.0-compatible controller interface
PHY independent training capability
Comprehensive set of design-for-test (DFT) features

Applications

Data center and networking
High performance computing (HPC)
Artificial intelligence (AI)
High-end graphics

Deliverables

Executable .run installation file, including GDSII, LEF Files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample verification environment, PHY data book, physical implementation guide, application notes, verification guide, installation guide, implementation checklist
The PHY Utility Block includes Verilog code, synthesis/STA constraints and scripts, sample verification environment, data book

Technical Specifications

Foundry, Node

TSMC N5, N3E - EFF, FF

Availability

Contact the Vendor

TSMC

Pre-Silicon: 3nm , 5nm

Request Info