Features a state-of-the-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environments. This architecture enables OPHYs to overcome issues with long-term impedance drift and clock phase drift, enabling impedance and clock phase updates without interrupting data traffic. Programmable timing at the OPHY boundary combines flexibility with analog precision, resulting in low read/write latency between the ORBIT Memory Controller (OMC) and the DRAM.
OPHYs are designed with subsystem and system-level considerations in mind. Built-in power management logic and advanced PLL design allow aggressive power state management and optimal system power usage. Tight integration with the ORBIT Memory Subsystem enables ActiveQoS bandwidth and latency control for maximum performance of the SoC memory subsystem. At the system level, OPHYs have been designed to minimize package substrate layer and PCB layer requirements, enabling usage in cost-sensitive applications.
