HBM3 PHY

Overview

Highest performance IP for graphics, AI/ML

The High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require the highest-bandwidth, low-latency memory solution. The memory subsystem PHY supports data rates up to 8.4Gbps per data pin, featuring 16 independent channels, for a total data width of 1024 bits. The PHY is designed for a 2.5D system with a silicon interposer to route signals between the 3D DRAM stack and PHY. The third-generation design is optimized for low power consumption and low PHY area. Cadence provides the complete solution including PHY, interposer, and package.

Key Features

Advanced clocking architecture minimizes clock jitter
DFI PHY Independent Mode for initialization and training
IEEE 1500 interface, Memory BIST feature, and loop-back function
Supports lane repair
Designed for optimized interposer routing

Benefits

Highest Performance
HBM3E up to 8.4Gbps per pin and HBM2E up to 3.6Gbps per pin
Low Latency
For data-intensive applications
Low Power and Area: Low-power control and advanced low-power modes with power down
Easy integration: PHY is hardened, and timing closed including all I/O and decoupling capacitors
Complete HBM Solution: Full system design including PHY, interposer, and package
Excellent Support: Access to Cadence expert SI/PI team to support customer designs

Block Diagram

Technical Specifications

Samsung

Pre-Silicon: 10nm

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