MSquare's HBM3 IP (the 3rd generation of High-Bandwidth Memory) is specifically tailored for applications that require high memory throughput and low latency, complying with the JESD238 memory standard. It includes both PHY and Memory Controller components, supporting HBM3 SDRAM speeds ranging from 4.8Gbps/pin to 6.4Gbps/pin. Flexible configurations are available, including PHY Only, PHY + Controller, and Controller Only, to accommodate diverse customer design specifications. Additionally, the chip's footprint and power consumption are highly competitive within the industry.
HBM3 PHY and Controller.
Overview
Key Features
- Consists PHY and Memory Controller.
- Optional add-on IPs to achieve best performance.
- Optimized for 7nm process.
- Supports speed up to 6.4Gbps/pin.
- Features integrated PLL and IO.
- Standard DFI 5.0 support for interoperability.
- Flexible configurations available: (PHY only), ( PHY + Controller) or (Controller only).
- Equipped with embedded MCU for flexibility to perform firmware-based training.
- PHY IP optionally supports interfacing to itself providing D2D interface solutions.
- Minimized footprint and power consumption.
Block Diagram
Technical Specifications
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