MSquare's HBM3 IP (the 3rd generation of High-Bandwidth Memory) is specifically tailored for applications that require high memory throughput and low latency, complying with the JESD238 memory standard. It includes both PHY and Memory Controller components, supporting HBM3 SDRAM speeds ranging from 4.8Gbps/pin to 6.4Gbps/pin. Flexible configurations are available, including PHY Only, PHY + Controller, and Controller Only, to accommodate diverse customer design specifications. Additionally, the chip's footprint and power consumption are highly competitive within the industry.
HBM3 PHY and Controller.
Overview
Key Features
- Designed for high memory throughput and low latency applications
- Consists PHY and Memory Controller
- Optimized for 12nm process
- Supports speed up to 6.4Gbps/pin
- Features integrated PLL and IO
- Flexible configurations available: (PHY only) or ( PHY + Controller) or (Controller only)
- Supports both firmware-based training and hardware-based training
- Optional Add-on IPs to achieve best performance
- Minimized footprint and power consumption
Technical Specifications
Related IPs
- Master and Slave SPI Bus Controller
- Universal Multi-port Memory Controller for RLDRAM2/3, DDR4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
- AHB Octal SPI Controller with PSRAM and XIP Support
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
- UCIe-S PHY and Controller