HBM2E DFI Assertion IP

Overview

Key Features

• Specification Compliance
  • Compliant with DFI version 4.0 or 5.0 Specifications.
  • Supports HBM2E devices compliant with JEDEC HBM2E DRAM Standard JESD235B and JESD235C.
  • Supports all Interface Groups.
  • Supports Write Transactions with Data mask
  • Supports DRAM Clock disabling feature.
  • Supports Data bit enable/disable feature.
  • Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
  • Supports frequency change protocol.
  • Supports Low power control features.
  • Supports Error signaling.
  • Supports DFI Read/Write Chip Select.
  • Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
  • Constantly monitors DFI behavior during simulation.
  • Protocol checker fully compliant with DFI 4.0 or 5.0 Specifications.
• Assertion IP features
  • Assertion IP includes:
  • System Verilog assertions
  • System Verilog assumptions
  • System Verilog cover properties
  • Synthesizable Verilog Auxiliary code
  • Support Master mode, Slave mode, Monitor mode and Constraint mode.
  • Supports Simulation mode (stimulus from SmartDV HBM2E VIP) and Formal mode (stimulus from Formal tool).
  • Rich set of parameters to configure HBM2E Assertion IP functionality.

Benefits

• Runs in every major formal and simulation environment.

Block Diagram

Deliverables

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.

Technical Specifications