The Hash Crypto Engine is flexible and optimized hash IP core compliant with FIPS 180-3 (HASH functions), FIPS 198 (HMAC function) and OSCCA (SM3).
With a flexible wrapper supporting a wide selection of programmable hashing modes (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SM3 and MD5) with HMAC and several options of data interface, the Hash Crypto Engine is an easy-to-use solution with predictable resources and performances on ASIC and FPGA.
Overview
The Hash Crypto Engine is easily portable to ASIC and FPGA. It supports a wide range of applications on various technologies. The unique architecture enables a high level of flexibility. The throughput and features required by a specific application can be taken into account in order to select the most optimal and compact configuration.
Hash Crypto Engine
Overview
Key Features
- ASIC and FPGA
- Supports:
- SHA-1
- SHA-224
- SHA-384
- SHA-512
- SM3
- MD5
- Supports HMAC
- Message padding in software or hardware
- Low power feature
- Data interface: AMBA (AHB/AXI) with optional DMA
- AMBA (APB, AXi-4 Lite) Configuration Interface
- Control interface: APB/AXI4-lite
Benefits
- Off-the-shelf, predictable and silicon-proven solution
- Logic footprint optimized to used hash functions
- Supports several hash functions
- Easy to integrate
- User-friendly Software API
- Portable and optimized to ASIC or FPGA technology
Block Diagram
Applications
- Digital signature
- Key derivation
Deliverables
- Netlist or RTL
- Scripts for synthesis
- Self-checking Testbench based on FIPS vectors
- Datasheet
- Integration guide
Technical Specifications
Maturity
Silicon proven
Availability
Now