Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates JPEG streams to RTP packets compliant with RFC 2435.
The JPEG2RTP can be directly connected to the output of a JPEG encoder to output RTP packets, which can subsequently be forwarded for UDP/IP or TCP/IP encapsulation. The hardware stack produces complete RTP packets, without the need for any host-processor assistance. Along with CAST’s UDP/IP hardware stack, the JPEG2RTP core is ideal for offloading the demanding task of RTP/UDP/IP encapsulation from a host processor, and enables JPEG video streaming even in processor-less SoC designs.
The core is easy to integrate in systems with or without a host processor. JPEG stream and RTP packet data are input/output via dedicated streaming-capable AXI4-Stream or Avalon-ST interfaces, enabling direct connection to hardware video encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by AXI4-Lite or Avalon-MM interface.
The JPEG2RTP core is available in RTL source or as a targeted FPGA netlist. Platforms integrating the core with JPEG encoder, UDP/IP, and eMAC cores, are also available from CAST, and can enable rapid development of video over IP systems.
The JPEG2RTP core is suitable for a wide variety of systems and devices featuring JPEG video streaming over IP networks. A sample block diagram of such systems is provided above.
