The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754R Standard). It is designed to provide a powerful floating-point functionality for low-power, low frequency applications.
The A2FH supports half precision operations in a 1- stage execution pipeline. The pipeline insures maximum performance in low-frequency applications, providing up to 200 MFLOPS on a 0.13u ASIC process. The host interface is clean and versatile, simplifying the interfacing to host processor pipelines.
IEEE-754R Compliance
The A2FH is designed to provide a powerful floating-point capability while minimizing die size cost. To minimize unnecessary design size, some of the rarely used features of the IEEE specification are not implemented directly in the hardware design. The following IEEE-defined operations are not directly supported in A2FH hardware, but can be supported with software support:
- Gradual Underflow
- Denormal Numbers
In place of gradual underflow, the A2FH implements a flush-to-zero approach when underflow occurs. This feature allows the A2FH to maintain a one-cycle throughput in all operand cases, and minimizes design size.
Optional Divide Unit
The divide unit within the A2FH design provides divide, square root, and remainder functions. In order to further minimize the design size, the A2FH can be synthesized with or without a divide unit. Many multi-media applications can be implemented without the use of divide functions. For customers who need the absolute minimum area, this option is a must.
