Half Precision IEEE-754R complete FPU for graphics processing
Overview
This block may be used to convert and existing single register stage into a stallable pipeline stage. It can also be used with synchronous RAM blocks, Register Files, etc. to convert them into stallable pipeline elements
Key Features
- Configurable for width
Deliverables
- verilog RTL and Testbench
Technical Specifications
Maturity
Multiple Uses
Availability
Now
Related IPs
- 2D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- High-performance 2D (sprite graphics) GPU IP combining high pixel processing capacity and minimum gate count.
- 2D (vector graphics) GPU IP Further advanced architecture for minimized CPU load and increased pixel performance in vector processing
- Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
- 2D Graphics Processor for Wearables/IoT
- Digital Signal Processor (DSP) for image processing