The eSi-HP-FP-Fused-Multiply-Add IP core implements half-precision (16-bit), IEEE 754 compliant, floating-point fused multiply and add operations.
Half precision, IEEE 754, floating point fused multiply add
Overview
Key Features
- Half-precision (16-bit) floating point fused multiply and add.
- IEEE 754 compliant.
- Full support for infinities, NaNs and denormals.
- Rounding is to the nearest even number.
- Status flags indicating invalid, overflow, underflow and inexact.
- Optional pipeline registers.
- Supports one operation per cycle.
Deliverables
- Verilog RTL
- Testbench
- Simulation and synthesis scripts
- Documentation
Technical Specifications
Maturity
Silicon proven in multiple products
Availability
Immediate
Related IPs
- Single precision, IEEE 754, floating point adder
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- Single precision, IEEE 754, floating point to integer conversion
- Single precision, IEEE 754, integer to floating point conversion