H.264 encoder

Overview

D2830 is a low-power consumption and small gate-count H.264 encoder up to CIF (352x288) @ 30fps.
The typical power consumption is about 10mw.

Key Features

  • Configurable profiles, fully compliant with ITU-T Recommendation H.264 | ISO/IEC 14496-10 Advanced Video Coding Standard (MPEG-4 Part 10). Scalable resolution up to 1920x1088P at 30fps
  • High compression efficiency
  • Patent-pending rate control: CBR and VBR
  • Patent-pending motion estimation engine
  • Programmable slice control
  • MV: -32 to +31
  • Half/Quarter pixel precision supported
  • Minimal CPU load
  • Easy integration with Jade¡¦s state-of-the-art Preprocess engine (Denoise, Rotation, Scaling etc.)
  • Optimized low-power and scalable architecture
  • AMBA bus
  • Simple API enables fast application development

Deliverables

  • Hardware
    • Verilog RTL
    • RTL simulation test data
    • Synthesis script templates (Synopsys Design Compiler, TCL-format)
    • Static Timing Analysis script templates (Synopsys PrimeTime)
    • Hardware test bench
  • Software
    • Hardware driver (eLinux or WinCE OS)
    • SW library (eLinux or WinCE OS)
    • API
    • Example code
  • Documents
    • Technical Reference Manual
    • RTL simulation report
    • RTL coverage report
    • API user manual

Technical Specifications

Foundry, Node
0.13G
Maturity
mature
Availability
Now
TSMC
In Production: 130nm G
Pre-Silicon: 130nm G
Silicon Proven: 130nm G
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Semiconductor IP