TMC's TM21745 is a decoder IP core that is compliant with ISO/IEC 14496-10 | ITU-T Rec.H.264.
Using TMC's original computer algorithm, we have realized a compact hardware IP that can be mounted on a low-cost FPGA while maintaining high image quality and high performance. It can be used for ASICs as well.
H.264/AVC 1080 60p Baseline Profile Decoder
Overview
Key Features
- Compact, high image quality and high speed processing
- Real-time processing of 1920x1080p, 60fps with a low-cost FPGA eg.) Xilinx Artix-7 series, Intel Cyclone V series
- 4K30p processing with a single core eg.) Xilinx Kintex UltraScale+ series, Intel Arria 10, Stratix 10 series
- Easy implementation
- Easy connection to memory area with AXI I/F
- Designed with hardware logic only, easy operation without CPU
- Low latency
- 10ms or less in combination with TMC decoder
- Flexible response to customer requests with options
- Multi channel
- ROI(Region of Interest)
- WDR(Wide Dynamic Range)
Benefits
- TMC's DMNA (Digital Media New Algorithm), our original mathematical algorithm, drastically reduces the total amounts of calculations & operations, and realizes high-speed processing, high-quality image output, and low power consumption.
Block Diagram
Applications
- Amusement
- Car-mounted system
- Digital camera / Digital video camera
- Low-delay transmission system
- Video camera / Surveillance camera / Web camera
Deliverables
- Encrypted RTL
- Datasheets
- Verification environment
- Synthesis constraint
- Bit accurate model