GNSS (GPS, Galileo, GLONASS, Beidou3, QZSS, SBAS) Ultra-low power RF Receiver IP

Overview

This GNSS RF Receiver IP is silicon-proven in TSMC40nm ULP process node, offers comprehensive support for all current satellite-based navigation systems, encompassing GPS (US), Galileo (EU), GLONASS (Russia), Beidou (China), QZSS (Japan), and SBAS. Tailored for battery-powered IoT and M2M applications, it concurrently accommodates L1/L2 and L5 frequencies.

Integrated within this IP are both integer-N (default) and dual-mode fractional-N frequency synthesizers, facilitating the utilization of a singular reference frequency across multiple modes. Its fully integrated Frequency Synthesizer (SX) features a wide-ranging VCO tuning capability, ensuring coverage across various frequency requirements and process corners. Moreover, it supports both single-system and multi-system operations.

This can be ported to any technology node subject to the availability of the RF front end. It can be supplied with the most stable firmware for accurate highly reliable location tracking along with support and upgrades.

This GNSS RF Receiver IP boasts high-level programmability, allowing optimization of power consumption and functionality across diverse scenarios. It is particularly well-suited for IoT and mobile tracking applications, thanks to its ultra-low power design. Furthermore, the RF IP incorporates an integrated reference clock buffer to ensure a stable reference frequency, thereby enhancing overall performance.

Key Features

  • Multiple Constellation tracking simultaneously
  • Fully integrated transceiver
  • Supports all constellations including GPS, Galileo, GLONASS, Beidou3, QZSS, NavIC, SBAS, A-GPS
  • Supports L1 and L5 bands
  • Proven in TSMC 40nm ULP RF CMOS
  • Can be ported to other process nodes.
  • Very low power consumption
  • Concurrent reception of multiple systems
  • Flexible frequency plan
  • Integrated DC offset cancellation
  • To implement low leakage, current the RF IP supports PMU (Power management Unit)
  • Exceedingly small die area
  • Integrated 8-bit quadrature SAR ADC for better blocker tolerance. Optional integrated LDOs to improve supply rejection

Block Diagram

GNSS (GPS, Galileo, GLONASS, Beidou3, QZSS, SBAS) Ultra-low power RF Receiver IP Block Diagram

Applications

  • Indoor Navigation.
  • Precise Tracking and Navigation
  • Infotainment systems
  • Avionics
  • Military and Defense
  • Wildlife conservation

Technical Specifications

Foundry, Node
65nm, 55ULP
Maturity
In Production
Availability
Immediate
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Semiconductor IP