GLOBALFOUNDRIES 28nm SLP sub-LVDS Receiver
Overview
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only.
Key Features
- Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
- 4 data channels / 1 clock channel integrated
- Maximum serial data rate per channel: 1Gbps
- Supports up to 8-bit CMOS parallel input (DVP input mode)
- Each channel configurable independently
- Controllable 100? on-chip termination resistor
- De-serializes the serial inputs with a fixed ratio (8)
Technical Specifications
Foundry, Node
GLOBALFOUNDRIES 28nm
Maturity
Silicon proven
GLOBALFOUNDRIES
Pre-Silicon:
28nm
FDSOI
,
28nm
HPP
,
28nm
LPH
,
28nm
SLP
Silicon Proven: 28nm SLP
Silicon Proven: 28nm SLP