GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arriving at the RX side in spite of different delays of TX and RX PCS FIFOs of different slices.
GLink Multi-Slice PCS is a configurable design for a specific multi-slice configuration. By specifying number of user interface and the corresponding data bus width, and whether different user interface would be merged into one GLink Slice, a specific GLink Multi-Slice PCS design could be provided, including RTL code with timing constraints and a testbench.
The Multi-Slice PCS is compatible with any revision of GLink IP, and it provides the error indication in case of alignment fail.
GLink Multi-Slice PCS
Overview
Key Features
- Align data buses of different GLink Slices
- Compatible with any revision of GLink IP
- VALID and READY handshake mechanism
- Support any data bus width
- Support multiple data buses merge to same GLink Slice
- Support at most eight combined Slices
- TX Multi-Slice PCS latency is 0 TX clock
- RX Multi-Slice PCS latency is default 1 RX clock
- Provide alignment fail status
Technical Specifications
Foundry, Node
TSMC
Maturity
Avaiable on request