General Purpose BandGap Reference

Overview

The agileREF consists of a bandgap reference core together with a bandgap reference voltage generator (VREF), VREF replica current generators and bias current generators. The number of output bias currents can be specified up to a maximum of 16 configurable outputs. There is an integrated test bus.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.

Key Features

  • Input Voltage Range: PDK VddIO
  • Programmable Output Voltage Range
  • Untrimmed Accuracy: 5%
  • Trimmed Accuracy (single point trim): 0.5%
  • Bias Current Output: 1uA to 100uA
  • Quiescent Current (Iq): 50uA typical
  • Customizable design for simple SoC integration

Benefits

  • Low Iq
  • - Low current consumption for power sensitive applications
  • Multiple Outputs
  • - Use as a single reference source for your SoC/ASIC

Block Diagram

General Purpose BandGap Reference Block Diagram

Applications

  • IoT, Security, Automotive, AI, SoCs, ASICs

Deliverables

  • Datasheet
  • Testing and Integration Guide
  • Verilog Models
  • Floorplan (LEF)
  • Timing models (LIB)
  • Netlist (CDL)
  • Layout (GDS)
  • Physical Verification Report
  • Design Report

Technical Specifications

Foundry, Node
Intel
Maturity
Available on request
Availability
Now
Intel Foundry
Pre-Silicon: 16nm
×
Semiconductor IP