GDDR4 Synthesizable Transactor provides a smart way to verify the GDDR4 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's GDDR4 Synthesizable Transactor is fully compliant with standard GDDR4Spec rev 04.pdf Specification and provides the following features.
GDDR4 Synthesizable Transactor
Overview
Key Features
- Supports 100% of GDDR4 protocol standard GDDR4Spec rev 04
- Supports all the GDDR4 commands as per the specs
- Supports all types of timing and protocol violation detection
- Supports all mode registers programming
- Supports double data rate architecture
- Supports programmable clock frequency of operation
- Supports single ended read strobe (RDQS) per byte
- Supports single ended write strobe (WDQS) per byte
- Supports quad or eight internal banks for concurrent operation
- Checks for following:
- Check-points include power on, initialization and power off rules
- State based rules, active command rules
- Read/write command rules etc
- All timing violations
- Supports programmable burst length: 8 only
- Supports data mask (DM) for masking write data
- Supports multiplexed addressing
- Supports auto precharge option for each burst access
- Supports auto refresh and self refresh modes
- Supports on‐die termination (ODT)
- Supports programmable offset for both driver and termination
- Supports parity and boundary scan
- Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the GDDR4 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes