IP Catalog > Analog IP > Clocking IP > PLL IP > Clock Generator PLL IP > Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz

Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz

Overview

A programmable fully digital PLL designed to lock to an incoming clock source and produce an output clock. It is ideal as a clock generator for digital designs, but not intended for analog blocks like ADC/DAC or SERDES clocking. This digital PLL has ultra-low area and low implementation charges due to predictable digital design.

Key Features

  • Ideal as a clock generator for digital design
  • Excellent frequency jitter performance
  • Ultra-low area fully digital PLL design
  • Patented glitch free frequency adjustment
  • Fine frequency precision with fractional divider
  • Low implementation charges due to predictable digital design
  • Can be implemented on all modern TSMC processes (HPC+ 28 nm, 16FFC 16 nm, N7+ 7 nm)

Benefits

  • Fully digital PLL design
  • Low implementation charges due to predictable digital design
  • Low complexity
  • Competitive price

Block Diagram

Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz Block Diagram

Applications

  • It is ideal as a clock generator for digital designs, but not intended for analog blocks like ADC/DAC or SERDES clocking. For example, SoC prototypes for mobile applications and IoT.

Deliverables

  • GDSII (100% DRC and LVS clean)
  • Verilog model
  • LEF
  • User integration Guidelines

Technical Specifications

Short description
Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz
Vendor
Vendor Name
Foundry, Node
TSMC 16FFC 16 nm
Maturity
Pre-Silicon 16FFC
Availability
Upon request.
TSMC
Pre-Silicon: 16nm
Request Info

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