Frac-N PLL on Samsung 8nm LN08LPP

Overview

PLLF0842X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.

It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).

The maximum output frequency of PLL is 4.5GHz.

Key Features

  • Operating junction temperature(TJ): -40°C ~ 125°C 
  • Output frequency range: 35.2MHz ~ 4.5GHz 
  • Duty ratio: 48 ~ 52% 
  • Power down mode 
  • Bypass mode (FOUT = FIN) 
  • Programmable dividers 
  • Glitch-free scaler 
  • On-chip loop filter

Benefits

  • Glitch-free scaler
  • Low Jitter
  • Low Power

Block Diagram

Frac-N PLL on Samsung 8nm LN08LPP Block Diagram

Applications

  • Mobile/Consumer

Deliverables

  • FE(Front-End) : LEF, LIBERTY, MODEL, TB FUNCTION, TB VECTOR GEN, TWRAP
  • BE(Back-End) : CIR, DFM, DRC, GDS, LVS

Technical Specifications

Short description
Frac-N PLL on Samsung 8nm LN08LPP
Vendor
Vendor Name
Foundry, Node
SF 8nm, LN08LPP
Samsung
Pre-Silicon: 8nm
×
Semiconductor IP